Leverage Intel's EMIB and Foveros Direct to build 12-reticle 3D stacked system-in-packages for advanced chip scaling

Intel is expanding its chip packaging strategy to include system-in-packages that cover the area of 12 reticles. This ambitious goal relies on combining two specific advanced packaging technologies: EMIB and Foveros Direct 3D. The company is mapping out the technical path required to achieve this scale, according to a report published by Tom's Hardware Premium on October 17, 2026.

In plain English

A reticle is the maximum size of a silicon wafer that a fabrication machine can process at one time. By connecting multiple dies across 12 reticles, Intel can create chips that are far larger than what a single manufacturing step allows. This approach lets engineers combine different specialized components into one powerful package without needing to shrink transistors further. It effectively bypasses physical limits on chip size by stacking and linking smaller pieces together.

The background

Tom's Hardware Premium subscribers gained access to an exhaustive report detailing these roadmaps earlier this month. The analysis highlights that Intel’s EMIB and Foveros technologies are continuing to mature over time. This maturation has attracted new customers who want to leverage these methods for building more sophisticated hardware offerings. The report maps out the specific steps Intel plans to take to reach the 12-reticle milestone using both technologies in tandem.

What changes now

The publication of this roadmap clarifies Intel’s long-term vision for advanced packaging. It signals that the company sees growth in customers adopting its proprietary interconnect and stacking solutions. This move suggests a shift toward larger, more complex system-in-packages rather than relying solely on traditional single-die scaling. The strategy aims to provide a clear path for manufacturers to build higher-performance systems using existing fabrication capabilities combined with advanced packaging.

Key terms explained

Advanced packaging involves connecting multiple semiconductor dies to function as a single unit. Teams usually evaluate whether their design benefits from 3D stacking or side-by-side interconnects. Check whether your architecture requires high bandwidth between components, which often favors vertical stacking. Consider if thermal management is a constraint, as denser packages generate heat in concentrated areas. Understanding these trade-offs helps engineers select the right packaging method for performance needs.

What to do and how to stay safe: Intel

• Review current hardware designs to see if advanced packaging could replace larger single dies.
• Monitor vendor announcements for new EMIB or Foveros-compatible components and tools.
• Evaluate thermal requirements for any system-in-package designs you plan to implement.
• Consult with packaging specialists to assess the feasibility of multi-reticle strategies for your projects.

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Frequently asked questions

What is the maximum size Intel plans for its new system-in-packages?

Intel plans to build system-in-packages the size of 12 reticles using EMIB and Foveros Direct 3D.

Which technologies will Intel use to achieve this packaging scale?

The company will use both EMIB and Foveros Direct 3D technologies to reach this goal.

Who has access to the full analysis of this roadmap?

Tom's Hardware Premium subscribers can read the exhaustive report on these roadmaps.